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1 RT8105 ds8105-03 april 2011 www.richtek.com features z z z z z operating with 5v or 12v supply voltage z z z z z drives all low cost n-mosfets z z z z z voltage mode pwm control z z z z z 300khz fixed frequency oscillator z z z z z fast transient response : ` ` ` ` ` high-speed gm amplifier ` ` ` ` ` full 0 to 100% duty ratio z z z z z internal soft-start z z z z z adaptive non-overlapping gate driver z z z z z over-current fault monitor on mosfet, no current sense resistor required z z z z z full-time over voltage protection z z z z z rohs compliant and halogen free 5v/12v synchronous buck pwm dc/dc controller general description the RT8105 is a high efficiency synchronous buck pwm controllers that generate logic-supply voltages in pc based systems. these high performance , single output devices include internal soft-start, frequency compensation networks and integrates all of the control, output adjustment, monitoring and protection functions into a single package. the device operating at fixed 300khz frequency provides an optimum compromise between efficiency, external component size, and cost. adjustable over-current protection (ocp) monitors the voltage drop across the r ds(on) of the lower mosfet for synchronous buck pwm dc/dc controller. the over- current function cycles the soft-start in 4-times hiccup mode to provide fault protection, and in an always hiccup mode for under-voltage protection. ordering information applications z graphic card z motherboard, desktop servers z ia equipments z telecomm equipments z high power dc/dc regulators pin configurations (top view) sop-8 phase boot ugate lgate gnd vcc ops fb 2 3 4 5 8 7 6 note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. marking information RT8105 gsymdnn RT8105gs : product number ymdnn : date code RT8105gs RT8105zs : product number ymdnn : date code RT8105zs RT8105 zsymdnn package type s : sop-8 RT8105 lead plating system g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free) www.datasheet.net/ datasheet pdf - http://www..co.kr/
2 RT8105 www.richtek.com ds8105-03 april 2011 functional pin description boot (pin 1) bootstrap supply pin for the upper gate driver. connect the bootstrap capacitor between boot pin and the phase pin. the bootstrap capacitor provides the charge to turn on the upper mosfet. ugate (pin 2) upper gate driver output. connect to the gate of high side power n-mosfet. this pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper mosfet has turned off. gnd (pin 3) both signal and power ground for the ic. all voltage levels are measured with respect to this pin. ties the pin directly to the low side mosfet source and ground plane with the lowest impedance. lgate (pin 4) lower gate drive output. connect to the gate of low side power n-mosfet. this pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower mosfet has turned off. vcc (pin 5) connect this pin to a well-decoupled 5v or 12v bias supply. it is also the positive supply for the lower gate driver, lgate. fb (pin 6) switcher feedback voltage. this pin is the inverting input of the error amplifier. fb senses the switcher output through an external resistor divider network. ops (ocset, por and shut-down) (pin 7) this pin provides multi-function of the over-current setting, ugate turn-on por sensing, and shut-down features. connecting a resistor (r ocset ) between ops and phase pins sets the over-current trip point. pulling the pin to ground resets the device and all external mosfets are turned off allowing the output voltage power rails to float. this pin is also used to detect v in in power on stage and issues an internal por signal. phase (pin 8) connect this pin to the source of the upper mosfet and the drain of the lower mosfet. typical application circuit 2%) (0.8v voltage reference internal : v ) r2 r3 (1 v v ref ref out + = boot vcc phase ugate ops lgate fb gnd 1 5 6 3 2 8 7 4 10 1f 3 h + 5 v t o + 1 2 v v o u t 0.1f 470f 1000fx3 32 68 3904 mu ml 0.1 to 0.33f 1f 200 to 1k RT8105 + 3 . 3 v / + 5 v / + 1 2 v b a t 5 4 r ocset r1 c1 c2 r2 r3 r4 c3 c4 c5 c6 to c8 d1 l1 q1 q2 q3 v i n disable > 0 0 r c r b o o t r u g a t e www.datasheet.net/ datasheet pdf - http://www..co.kr/
3 RT8105 ds8105-03 april 2011 www.richtek.com function block diagram gate control logic ops gnd lgate boot ugate phase ph_m en soft-start & fault logic + - oscillator (300khz) power on reset vcc eo fb reference 0.8v ref bias & regulators (3v_logic & 3vdd_analog) + - + - 1.5v 0.1v vcc gm + - + - 0.6v uv_s - + oc 3v 0.4v 40ua + - ovp 1v 1.3v i oc v oc www.datasheet.net/ datasheet pdf - http://www..co.kr/
4 RT8105 www.richtek.com ds8105-03 april 2011 electrical characteristics (v cc = 5v/12v, t a = 25 c, unless otherwise specified) absolute maximum ratings (note 1) z supply voltage, v cc -------------------------------------------------------------------------------------- 16v z boot to phase ------------------------------------------------------------------------------------------ 15v z ugate to phase dc ------------------------------------------------------------------------------------------------------------- ? 0.3v to (v boot-phase + 0.3v) <20ns -------------------------------------------------------------------------------------------------------- ? 5v to (v boot-phase + 5v) z phase to gnd dc ------------------------------------------------------------------------------------------------------------- ? 0.5v to 15v <20ns -------------------------------------------------------------------------------------------------------- ? 5v to 25v z lgate to gnd dc ------------------------------------------------------------------------------------------------------------- ? 0.3v to (v cc + 0.3v) <20ns -------------------------------------------------------------------------------------------------------- ? 5v to (v cc + 5v) z input, output or i/o v oltage -------------------------------------------------------------------- --------- gnd-0.3v to 7v z power dissipation, p d @ t a = 25 c (note 2) sop-8 -------------------------------------------------------------------------------------------------------- 0.625w z package thermal resistance sop-8, ja -------------------------------------------------------------------------------------------------- 160 c/w z junction temperature ------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) --------------------------------------------------------------- 260 c z storage temperature range ---------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------------ 2kv mm (ma chine mode) -------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) z supply voltage, v cc -------------------------------------------------------------------------------------- 5v 5%,12v 10% z junction temperature range ---------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------------------------------------------------------- ? 20 c to 85 c parameter symbol test conditions min typ max unit ic supply voltage v cc 4.75 -- 13.2 v nominal supply current i cc ugate and lgate open -- 6 15 ma power-on reset por threshold v ccrth v cc rising 3.8 4.1 4.35 v hysteresis v cchys 0.35 0.5 -- v switcher reference reference voltage v ref v cc = 12v 0.784 0.8 0.816 v oscillator free running frequency f os c v cc = 12v 250 300 350 khz ramp amplitude v osc v cc = 12v -- 1.5 -- v p-p to be continued www.datasheet.net/ datasheet pdf - http://www..co.kr/
5 RT8105 ds8105-03 april 2011 www.richtek.com parameter symbol test conditions min typ max unit error amplifier (gm) e/a transconductance g m -- 0.2 -- ms open loop dc gain a o -- 90 -- db pwm controller gate drivers (v cc = 12v) upper gate source i ugate v boot ? v phase = 12v, v ugate ? v phase = 6v 0.6 1 -- a upper gate sink r ugate v boot ? v phase = 12v, v ugate ? v phase = 1v -- 4 8 lower gate source i lgate v cc = 12v, v lgate = 6v 0.6 1 -- a lower gate sink r lgate v cc = 12v, v lgate = 1v -- 3 5 protection fb under-voltage trip fbuvt fb falling 70 75 80 % oc current source i oc v phase = 0v 35 40 45 a pre-ovp threshold (before por) v ovp1 v cc = 3v, sweep v fb -- 1.1 1.3 v ovp threshold (after por) v ovp2 v cc = 5v, sweep v fb 1 1.3 1.5 v soft-start interval t ss -- 3.5 -- ms note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. www.datasheet.net/ datasheet pdf - http://www..co.kr/
6 RT8105 www.richtek.com ds8105-03 april 2011 typical operating characteristics power on from v in time (2ms/div) v out (1v/div) ugate (20v/div) v in = v cc = 12v, v out = 1.5v, i load = 20a v in (5v/div) lgate (20v/div) disable from ops time (40 s/div) v out (1v/div) ugate (20v/div) v in = v cc = 12v, v out = 1.5v, i load = 5a ops (2v/div) lgate (20v/div) enable from ops time (2ms/div) v out (1v/div) ugate (20v/div) v in = v cc = 12v, v out = 1.5v, i load = 5a ops (2v/div) lgate (20v/div) over voltage protection time (20 s/div) ugate (10v/div) v in = 5v, v cc = 12v, v out = 1.5v, no load fb (500mv/div) lgate (10v/div) under voltage protection time (20 s/div) ugate (10v/div) v in = 5v, v cc = 12v, v out = 1.5v, no load fb (500mv/div) lgate (10v/div) v in and v cc power sequence time (2ms/div) v out (1v/div) ugate (20v/div) v in = v cc = 12v, v out = 1.5v, i load = 20a v cc (10v/div) v in (5v/div) v in comes after v cc www.datasheet.net/ datasheet pdf - http://www..co.kr/
7 RT8105 ds8105-03 april 2011 www.richtek.com over current protection time (20 s/div) ugate (20v/div) v in = v cc = 12v, v out = 1.5v, r ocset = 15.4k inductor current (20a/div) lgate (20v/div) v out (2v/div) low side mosfet r ds(on) = 9m short circuit over current protection time (2ms/div) ugate (50v/div) v in = v cc = 12v, r ocset = 15k inductor current (20a/div) lgate (20v/div) v out (1v/div) low side mosfet r ds(on) = 6m short circuit output terminal than power up reference voltage vs. temperature 0.784 0.788 0.792 0.796 0.800 0.804 0.808 0.812 0.816 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) reference voltage (v) v in = v cc = 5v, no load switching frequency vs. temperature 200 220 240 260 280 300 320 340 360 380 400 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) switching frequency (khz) 1 v in = v cc = 5v, no load www.datasheet.net/ datasheet pdf - http://www..co.kr/
8 RT8105 www.richtek.com ds8105-03 april 2011 application information RT8105 is a voltage-mode single phase synchronous buck controller with embedded mosfet drivers. this part provides complete protection functions such as over voltage protection, under voltage protection and over current protection. inductor current information is sensed by the r ds(on) of the low side mosfet. the over current protection threshold can be simply programmed by a resistor. in addition, the compensation circuit is implemented internally to minimize the external component count. vcc power on reset and v in detection once vcc exceeds its power on reset rising threshold v ccrth , ugate will output continuous pulses (~10khz, 1% duty cycle) for converter input voltage v in detection. figure 1 and figure 2 illustrate the operation of v in detection for RT8105. v in is recognized ready by detecting the voltage pulses at vos pin exceed 1.5v for four times (both rising edge + falling edge for counter increment = 1). once v in is recognized ready, controller will initiates the soft start operation. since a 40 a current will continuously flow through r ocset , r ocset must be lower than 37.5k for the correct v in detection function. controller will not initiate soft start if r ocset is higher than this value because v in will not be recognized ready. figure 1. v in detection function soft start once v in is recognized ready, lgate will go high for a short period of time to discharge the pre-biased voltage at the output capacitor. after that, controller will initiate the soft sta rt operation. RT8105 provides soft start function internally. the soft start function is used to prevent the large inrush current while converter is powered up. the fb signal will track the internal soft start signal, which is controlled by an internal digital counter and ramps up from zero in a monotone during soft start period. therefore the duty cycle of ugate signal will increase gradually and so does the input current. the typical soft-start duration is 3ms. over current protection (ocp) figure 2 shows the over current protection (ocp) scheme of RT8105. a resistor r ocset connected from phase pin to ops pin sets the threshold. an internal current source, i oc (40 a typically), flowing through r ocset determines the ocp trip point i ocset , which can be calculated using the following equation : ocset ocset ds(on) 40ua r 0.4 i r of the low side mosfet ? because the r ds(on) of mosfet increases with temperature, it is necessary to take this thermal effect into consideration in calculating ocp point. figure 2. over current protection scheme + - 3v i oc r ocset + - i oc x r ocset v in q1 q2 l + - i d x r ds(on) oc comparator + 0.4v ops phase in addition, note that the ocp threshold is very sensitive to the parasitic capacitance at ops pin. parasitic capacitance or the drain-to-source capacitance of the small mosfet (for shutdown function) will have influence on the ocp threshold. it is recommended to use small signal bjt for shutdown function. in addition, it is also recommended to place r ocset close to ic to minimize the trace parasitic. when ocp is tripped, both ugate and lgate will go low to stop the energy transfer to the load. controller will - + + - oc phase ugate ops 1.5v 10pf q2 r ocset cparasitic disable internal counter will count (v ops > 1.5v) four times (rising & falling) to recognize v in is ready. 3v + - i oc v oc v in detection counter www.datasheet.net/ datasheet pdf - http://www..co.kr/
9 RT8105 ds8105-03 april 2011 www.richtek.com try to restart in a hiccupped way. figure 3 shows the hiccupped over current protection. only four times of hiccup is allowed in over current protection. if over current condition still exist after four times of hiccup, controller will be latched. figure 3. hiccupped over current protection 0a 0v 2v 4v internal ss inductor current t1 t2 t3 time count = 1 count = 2 overload applied t0 t4 count = 3 count = 4 over voltage protection (ovp) the feedback voltage is continuously monitored for over voltage protection. when ovp is tripped, lgate will go high and ugate will go low to discharge the output capacitor. RT8105 provides full-time over voltage protection whenever soft start completes or not. over voltage protection has two operating conditions: before soft start completes and after soft start completes. each condition is described as follows. before soft start completes, the typical ovp threshold is 137.5% of the internal reference voltage v ref . RT8105 provides non-latched ovp before soft start completes. the controller will return to normal operation if over voltage condition is removed. after soft start completes, however, the ovp threshold is typically 162.5% of v ref . RT8105 provides latched ovp after soft start completes. the controller can only be reset if vcc por is exceeded again. under voltage protection (uvp) the feedback voltage is also monitored for under voltage protection. the under voltage protection has 15us triggered delay. when uvp is tripped, both ugate and lgate will go low. unlike ocp, uvp is not a latched protection; controller will always try to restart in a hiccupped way. out in out in s l v l(v v ) vf i =? enable/disable the controller can be disabled by pulling ops pin to ground. the enable/disable function can be implemented by connecting a mosfet or bjt to ops pin. it is recommended to use small signal mosfet/bjt to implement the enable/disable function. output inductor selection the selection of output inductor depends on the efficiency, output current and operating frequency. low inductance value can have fast transient response, but the associated large current ripple will cause large output ripple voltage and decrease the efficiency. in general, a 20% to 40% of inductor ripple current percentage ( i l / i out ) is preferred in practical application. the minimum inductance can be determined as follows : where : v in = input voltage v out = output voltage i l = inductor current ripple f s = switching frequency output capacitor selection the selection of output capacitor depends on the inductor ripple current, the output ripple voltage and the amount of voltage under shoot during transient. the output ripple voltage is a function of both the capacitance and the equivalent series resistance (esr) r c . the output ripple voltage can be expressed as follows : 2 t2 t1 s ol out l l out o l out oc or out d)t (1 c v 8 1 rc i i v dt ic c 1 rc i v v v v ? + = + = + = where v or is caused by esr, and v oc is related to the capacitance value. for electrolytic capacitor application, major of the output voltage ripple is typically contributed by the esr. therefore, the output voltage ripple can be simplified as follows : v out = i l x r c www.datasheet.net/ datasheet pdf - http://www..co.kr/
10 RT8105 www.richtek.com ds8105-03 april 2011 (a) d) d(1 i irms out ? = therefore the esr can be determined for a given output voltage ripple requirement. input capacitor selection the selection of input capacitor depends on the maximum ripple current capability. referred to figure 1, the buck converter draws pulsed current from the input capacitor during s1 is turned on. rms value of the ripple current flowing through the input capacitor can be expressed as follows : the input capacitor must be able to handle this rms current. it is recommended to add ceramic capacitor and placed physically close to the drain of the high side mosfet. this can effectively reduce the input ripple voltage. control loop stability RT8105 utilizes operational transconductance amplifier (ota) as the error amplifier and implements the compensation network internally. figure 4 shows the internal type ii compensator, which provides two poles and one zero to the control loop. figure 4. internal type ii compensator v out c 2 c 1 r 1 gm figure 5 illustrates the system bode plot. the close loop gain is the sum of the modulation gain and the compensation gain. the goal is to obtain the required crossover frequency with sufficient phase margin. the crossover frequency is preferred to be 1/10 to 1/5 of the switching frequency. the preferred phase margin is greater than 45 . because RT8105 utilizes internal compensation, the location of f z , f p and the gain at mid-frequency provided by the compensator are fixed. therefore the inductance, output capacitance and especially the esr of the output capacitor should be carefully selected to avoid stability issue. the esr can not be too small, or the system will have stability problem. if the location of the zero contributed by esr is far away from that of the lc double pole, the system will not have sufficient phase margin. it is recommended to choose output capacitor with proper esr value to meet the stability requirement. figure 5. system bode plot (db) gain (log scale) freq. f lc f esr f z f p f cross modulator compensator close loop gm ? r1 ? (voltage divider ration) pcb layout considerations pcb layout is critical to high-current high-frequency switching converter design. a good layout can help the controller to function properly and obtain better performance. on the other hand, the circuit may have more power loss, pool performance and even malfunction if without a carefully layout. in order to obtain better performance, the general guidelines of pcb layout are listed as follows. ` power stage components should be placed first. place the input bulk capacitors close to the high side power mosfets, and then locate the output inductor then finally the output capacitors. one of the poles is located at low frequency to increase the low frequency gain to improve the dc regulation accuracy. the location of the other pole and the single zero can be calculated as follows : zp 11 f; f c1 c2 2r1c2 2r1 c1+ c2 == ?? ?? ?? the transconductance and the internal compensation values are : gm = 0.2ma/v, r1 75k , c1 2.5nf, c2 10pf. the gain of the internal compensator at middle frequency can be calculated as follows : g mid-freq. = gm x r1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
11 RT8105 ds8105-03 april 2011 www.richtek.com ` placing the ceramic capacitors physically close to the drain of the high side mosfet. this can reduce the input voltage drop when high side mosfet is turned on. ` keep the high-current loops as short as possible. the current transition between mosfets usually causes di/dt voltage spike due to the parasitic components on pcb trace and component lead. therefore, making the trace length between power mosfets and inductors wide and short can reduce the voltage spike and also reduce emi. ` make mosfet gate driver path as short as possible. since the gate driver uses high-current pulses to switch on/off power mosfet, the driver path must be short to reduce the trace inductance. this is especially important for low side mosfet because this can reduce the possibility of shoot-through. besides, also make the width of gate driving path as wide as possible to reduce the trace resistance. ` provide enough copper area around power mosfets to help heat dissipation. using thick copper also reduces the trace resistance and inductance to have better performance. ` the output capacitors should be placed physically close to the load. this can minimize the trace parasitic components and improve transient response. ` the feedback voltage divider resistor must be placed close to fb pin because it is noise-sensitive. ` r ocset should be placed close to ic. ` the small signal mosfet/bjt used to shutdown the controller should be placed close to ic to minimize the trace parasitic components. ` voltage feedback path must away from switching nodes. the switching nodes, such as the interconnection between high side mosfet, low side mosfet and inductor, is extremely noisy. feedback path must away from this kind of noisy node to avoid noise pick-up. ` a multi-layer pcb design is recommended. use one single layer as the ground and have separate layers for power rail or signal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
12 RT8105 www.richtek.com ds8105-03 april 2011 richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050 www.datasheet.net/ datasheet pdf - http://www..co.kr/

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